
struct-yz:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400570 <_init>:
  400570:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400574:	910003fd 	mov	x29, sp
  400578:	94000040 	bl	400678 <call_weak_fn>
  40057c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400580:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400590 <.plt>:
  400590:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400594:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xfda4>
  400598:	f947fe11 	ldr	x17, [x16, #4088]
  40059c:	913fe210 	add	x16, x16, #0xff8
  4005a0:	d61f0220 	br	x17
  4005a4:	d503201f 	nop
  4005a8:	d503201f 	nop
  4005ac:	d503201f 	nop

00000000004005b0 <strlen@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  4005b4:	f9400211 	ldr	x17, [x16]
  4005b8:	91000210 	add	x16, x16, #0x0
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__libc_start_main@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  4005c4:	f9400611 	ldr	x17, [x16, #8]
  4005c8:	91002210 	add	x16, x16, #0x8
  4005cc:	d61f0220 	br	x17

00000000004005d0 <memset@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  4005d4:	f9400a11 	ldr	x17, [x16, #16]
  4005d8:	91004210 	add	x16, x16, #0x10
  4005dc:	d61f0220 	br	x17

00000000004005e0 <__gmon_start__@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  4005e4:	f9400e11 	ldr	x17, [x16, #24]
  4005e8:	91006210 	add	x16, x16, #0x18
  4005ec:	d61f0220 	br	x17

00000000004005f0 <abort@plt>:
  4005f0:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  4005f4:	f9401211 	ldr	x17, [x16, #32]
  4005f8:	91008210 	add	x16, x16, #0x20
  4005fc:	d61f0220 	br	x17

0000000000400600 <puts@plt>:
  400600:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  400604:	f9401611 	ldr	x17, [x16, #40]
  400608:	9100a210 	add	x16, x16, #0x28
  40060c:	d61f0220 	br	x17

0000000000400610 <printf@plt>:
  400610:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  400614:	f9401a11 	ldr	x17, [x16, #48]
  400618:	9100c210 	add	x16, x16, #0x30
  40061c:	d61f0220 	br	x17

0000000000400620 <putchar@plt>:
  400620:	d0000090 	adrp	x16, 412000 <strlen@GLIBC_2.17>
  400624:	f9401e11 	ldr	x17, [x16, #56]
  400628:	9100e210 	add	x16, x16, #0x38
  40062c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400630 <_start>:
  400630:	d280001d 	mov	x29, #0x0                   	// #0
  400634:	d280001e 	mov	x30, #0x0                   	// #0
  400638:	aa0003e5 	mov	x5, x0
  40063c:	f94003e1 	ldr	x1, [sp]
  400640:	910023e2 	add	x2, sp, #0x8
  400644:	910003e6 	mov	x6, sp
  400648:	580000c0 	ldr	x0, 400660 <_start+0x30>
  40064c:	580000e3 	ldr	x3, 400668 <_start+0x38>
  400650:	58000104 	ldr	x4, 400670 <_start+0x40>
  400654:	97ffffdb 	bl	4005c0 <__libc_start_main@plt>
  400658:	97ffffe6 	bl	4005f0 <abort@plt>
  40065c:	00000000 	.inst	0x00000000 ; undefined
  400660:	00400d94 	.word	0x00400d94
  400664:	00000000 	.word	0x00000000
  400668:	00400e90 	.word	0x00400e90
  40066c:	00000000 	.word	0x00000000
  400670:	00400f10 	.word	0x00400f10
  400674:	00000000 	.word	0x00000000

0000000000400678 <call_weak_fn>:
  400678:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xfda4>
  40067c:	f947f000 	ldr	x0, [x0, #4064]
  400680:	b4000040 	cbz	x0, 400688 <call_weak_fn+0x10>
  400684:	17ffffd7 	b	4005e0 <__gmon_start__@plt>
  400688:	d65f03c0 	ret
  40068c:	00000000 	.inst	0x00000000 ; undefined

0000000000400690 <deregister_tm_clones>:
  400690:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400694:	9103a000 	add	x0, x0, #0xe8
  400698:	d0000081 	adrp	x1, 412000 <strlen@GLIBC_2.17>
  40069c:	9103a021 	add	x1, x1, #0xe8
  4006a0:	eb00003f 	cmp	x1, x0
  4006a4:	540000a0 	b.eq	4006b8 <deregister_tm_clones+0x28>  // b.none
  4006a8:	90000001 	adrp	x1, 400000 <_init-0x570>
  4006ac:	f9479821 	ldr	x1, [x1, #3888]
  4006b0:	b4000041 	cbz	x1, 4006b8 <deregister_tm_clones+0x28>
  4006b4:	d61f0020 	br	x1
  4006b8:	d65f03c0 	ret
  4006bc:	d503201f 	nop

00000000004006c0 <register_tm_clones>:
  4006c0:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  4006c4:	9103a000 	add	x0, x0, #0xe8
  4006c8:	d0000081 	adrp	x1, 412000 <strlen@GLIBC_2.17>
  4006cc:	9103a021 	add	x1, x1, #0xe8
  4006d0:	cb000021 	sub	x1, x1, x0
  4006d4:	9343fc21 	asr	x1, x1, #3
  4006d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006dc:	9341fc21 	asr	x1, x1, #1
  4006e0:	b40000a1 	cbz	x1, 4006f4 <register_tm_clones+0x34>
  4006e4:	90000002 	adrp	x2, 400000 <_init-0x570>
  4006e8:	f9479c42 	ldr	x2, [x2, #3896]
  4006ec:	b4000042 	cbz	x2, 4006f4 <register_tm_clones+0x34>
  4006f0:	d61f0040 	br	x2
  4006f4:	d65f03c0 	ret

00000000004006f8 <__do_global_dtors_aux>:
  4006f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006fc:	910003fd 	mov	x29, sp
  400700:	f9000bf3 	str	x19, [sp, #16]
  400704:	d0000093 	adrp	x19, 412000 <strlen@GLIBC_2.17>
  400708:	3943a260 	ldrb	w0, [x19, #232]
  40070c:	35000080 	cbnz	w0, 40071c <__do_global_dtors_aux+0x24>
  400710:	97ffffe0 	bl	400690 <deregister_tm_clones>
  400714:	52800020 	mov	w0, #0x1                   	// #1
  400718:	3903a260 	strb	w0, [x19, #232]
  40071c:	f9400bf3 	ldr	x19, [sp, #16]
  400720:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400724:	d65f03c0 	ret

0000000000400728 <frame_dummy>:
  400728:	17ffffe6 	b	4006c0 <register_tm_clones>

000000000040072c <test>:
  40072c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400730:	910003fd 	mov	x29, sp
  400734:	f9000fa0 	str	x0, [x29, #24]
  400738:	f9400fa0 	ldr	x0, [x29, #24]
  40073c:	52800c21 	mov	w1, #0x61                  	// #97
  400740:	39000001 	strb	w1, [x0]
  400744:	f9400fa0 	ldr	x0, [x29, #24]
  400748:	90000001 	adrp	x1, 400000 <_init-0x570>
  40074c:	913d0021 	add	x1, x1, #0xf40
  400750:	f9000401 	str	x1, [x0, #8]
  400754:	f9400fa0 	ldr	x0, [x29, #24]
  400758:	f9400400 	ldr	x0, [x0, #8]
  40075c:	f90017a0 	str	x0, [x29, #40]
  400760:	f9400fa0 	ldr	x0, [x29, #24]
  400764:	f9400400 	ldr	x0, [x0, #8]
  400768:	f90013a0 	str	x0, [x29, #32]
  40076c:	f94017a0 	ldr	x0, [x29, #40]
  400770:	39400000 	ldrb	w0, [x0]
  400774:	2a0003e6 	mov	w6, w0
  400778:	f94017a0 	ldr	x0, [x29, #40]
  40077c:	b9400401 	ldr	w1, [x0, #4]
  400780:	f94017a0 	ldr	x0, [x29, #40]
  400784:	b9400802 	ldr	w2, [x0, #8]
  400788:	f94017a0 	ldr	x0, [x29, #40]
  40078c:	39404000 	ldrb	w0, [x0, #16]
  400790:	2a0003e3 	mov	w3, w0
  400794:	90000000 	adrp	x0, 400000 <_init-0x570>
  400798:	913d6000 	add	x0, x0, #0xf58
  40079c:	f94013a5 	ldr	x5, [x29, #32]
  4007a0:	2a0303e4 	mov	w4, w3
  4007a4:	2a0203e3 	mov	w3, w2
  4007a8:	2a0103e2 	mov	w2, w1
  4007ac:	2a0603e1 	mov	w1, w6
  4007b0:	97ffff98 	bl	400610 <printf@plt>
  4007b4:	52800000 	mov	w0, #0x0                   	// #0
  4007b8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4007bc:	d65f03c0 	ret

00000000004007c0 <f>:
  4007c0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4007c4:	910003fd 	mov	x29, sp
  4007c8:	90000000 	adrp	x0, 400000 <_init-0x570>
  4007cc:	913da000 	add	x0, x0, #0xf68
  4007d0:	97ffff8c 	bl	400600 <puts@plt>
  4007d4:	52800020 	mov	w0, #0x1                   	// #1
  4007d8:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4007dc:	d65f03c0 	ret

00000000004007e0 <test_pf>:
  4007e0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4007e4:	910003fd 	mov	x29, sp
  4007e8:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  4007ec:	9103c000 	add	x0, x0, #0xf0
  4007f0:	90000001 	adrp	x1, 400000 <_init-0x570>
  4007f4:	911f0021 	add	x1, x1, #0x7c0
  4007f8:	f9000001 	str	x1, [x0]
  4007fc:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400800:	9103c000 	add	x0, x0, #0xf0
  400804:	f9400000 	ldr	x0, [x0]
  400808:	d63f0000 	blr	x0
  40080c:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400810:	9103c000 	add	x0, x0, #0xf0
  400814:	90000001 	adrp	x1, 400000 <_init-0x570>
  400818:	911f0021 	add	x1, x1, #0x7c0
  40081c:	f9000001 	str	x1, [x0]
  400820:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400824:	9103c000 	add	x0, x0, #0xf0
  400828:	f9400000 	ldr	x0, [x0]
  40082c:	d63f0000 	blr	x0
  400830:	97ffffe4 	bl	4007c0 <f>
  400834:	d503201f 	nop
  400838:	a8c17bfd 	ldp	x29, x30, [sp], #16
  40083c:	d65f03c0 	ret

0000000000400840 <re>:
  400840:	d10043ff 	sub	sp, sp, #0x10
  400844:	52800020 	mov	w0, #0x1                   	// #1
  400848:	b90003e0 	str	w0, [sp]
  40084c:	52800040 	mov	w0, #0x2                   	// #2
  400850:	b90007e0 	str	w0, [sp, #4]
  400854:	52800060 	mov	w0, #0x3                   	// #3
  400858:	b9000be0 	str	w0, [sp, #8]
  40085c:	52800080 	mov	w0, #0x4                   	// #4
  400860:	b9000fe0 	str	w0, [sp, #12]
  400864:	b9400fe0 	ldr	w0, [sp, #12]
  400868:	910043ff 	add	sp, sp, #0x10
  40086c:	d65f03c0 	ret

0000000000400870 <foo>:
  400870:	92fc0000 	mov	x0, #0x1fffffffffffffff    	// #2305843009213693951
  400874:	d65f03c0 	ret

0000000000400878 <foo2>:
  400878:	92fc0000 	mov	x0, #0x1fffffffffffffff    	// #2305843009213693951
  40087c:	d65f03c0 	ret

0000000000400880 <foo3>:
  400880:	d2800000 	mov	x0, #0x0                   	// #0
  400884:	d65f03c0 	ret

0000000000400888 <T>:
  400888:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40088c:	910003fd 	mov	x29, sp
  400890:	f9000bf3 	str	x19, [sp, #16]
  400894:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400898:	91018000 	add	x0, x0, #0x60
  40089c:	f9400400 	ldr	x0, [x0, #8]
  4008a0:	f9001fa0 	str	x0, [x29, #56]
  4008a4:	90000000 	adrp	x0, 400000 <_init-0x570>
  4008a8:	913e2000 	add	x0, x0, #0xf88
  4008ac:	f9001ba0 	str	x0, [x29, #48]
  4008b0:	90000000 	adrp	x0, 400000 <_init-0x570>
  4008b4:	913f0001 	add	x1, x0, #0xfc0
  4008b8:	910083a0 	add	x0, x29, #0x20
  4008bc:	b9400022 	ldr	w2, [x1]
  4008c0:	b9000002 	str	w2, [x0]
  4008c4:	b8402021 	ldur	w1, [x1, #2]
  4008c8:	b8002001 	stur	w1, [x0, #2]
  4008cc:	52800200 	mov	w0, #0x10                  	// #16
  4008d0:	b9002fa0 	str	w0, [x29, #44]
  4008d4:	f9401ba0 	ldr	x0, [x29, #48]
  4008d8:	97ffff36 	bl	4005b0 <strlen@plt>
  4008dc:	aa0003f3 	mov	x19, x0
  4008e0:	910083a0 	add	x0, x29, #0x20
  4008e4:	97ffff33 	bl	4005b0 <strlen@plt>
  4008e8:	aa0003e1 	mov	x1, x0
  4008ec:	90000000 	adrp	x0, 400000 <_init-0x570>
  4008f0:	913e4000 	add	x0, x0, #0xf90
  4008f4:	aa0103e6 	mov	x6, x1
  4008f8:	d28000c5 	mov	x5, #0x6                   	// #6
  4008fc:	aa1303e4 	mov	x4, x19
  400900:	d2800103 	mov	x3, #0x8                   	// #8
  400904:	d2800102 	mov	x2, #0x8                   	// #8
  400908:	b9402fa1 	ldr	w1, [x29, #44]
  40090c:	97ffff41 	bl	400610 <printf@plt>
  400910:	f9401fa0 	ldr	x0, [x29, #56]
  400914:	f9400400 	ldr	x0, [x0, #8]
  400918:	f9400bf3 	ldr	x19, [sp, #16]
  40091c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400920:	d65f03c0 	ret

0000000000400924 <fxxx>:
  400924:	d10043ff 	sub	sp, sp, #0x10
  400928:	52800060 	mov	w0, #0x3                   	// #3
  40092c:	b9000fe0 	str	w0, [sp, #12]
  400930:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400934:	9101c000 	add	x0, x0, #0x70
  400938:	b9400000 	ldr	w0, [x0]
  40093c:	910043ff 	add	sp, sp, #0x10
  400940:	d65f03c0 	ret

0000000000400944 <iii>:
  400944:	12800000 	mov	w0, #0xffffffff            	// #-1
  400948:	d65f03c0 	ret

000000000040094c <print_ix>:
  40094c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400950:	910003fd 	mov	x29, sp
  400954:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400958:	9101e000 	add	x0, x0, #0x78
  40095c:	b9400401 	ldr	w1, [x0, #4]
  400960:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400964:	9101e000 	add	x0, x0, #0x78
  400968:	b9400802 	ldr	w2, [x0, #8]
  40096c:	90000000 	adrp	x0, 400000 <_init-0x570>
  400970:	913f2000 	add	x0, x0, #0xfc8
  400974:	52800003 	mov	w3, #0x0                   	// #0
  400978:	97ffff26 	bl	400610 <printf@plt>
  40097c:	d503201f 	nop
  400980:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400984:	d65f03c0 	ret

0000000000400988 <invoke>:
  400988:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40098c:	910003fd 	mov	x29, sp
  400990:	97ffffac 	bl	400840 <re>
  400994:	2a0003e1 	mov	w1, w0
  400998:	90000000 	adrp	x0, 400000 <_init-0x570>
  40099c:	913fe000 	add	x0, x0, #0xff8
  4009a0:	97ffff1c 	bl	400610 <printf@plt>
  4009a4:	97ffffb3 	bl	400870 <foo>
  4009a8:	aa0003e1 	mov	x1, x0
  4009ac:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  4009b0:	91006000 	add	x0, x0, #0x18
  4009b4:	97ffff17 	bl	400610 <printf@plt>
  4009b8:	97ffffb0 	bl	400878 <foo2>
  4009bc:	aa0003e1 	mov	x1, x0
  4009c0:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  4009c4:	9100e000 	add	x0, x0, #0x38
  4009c8:	97ffff12 	bl	400610 <printf@plt>
  4009cc:	97ffffad 	bl	400880 <foo3>
  4009d0:	aa0003e1 	mov	x1, x0
  4009d4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  4009d8:	91016000 	add	x0, x0, #0x58
  4009dc:	97ffff0d 	bl	400610 <printf@plt>
  4009e0:	97ffffaa 	bl	400888 <T>
  4009e4:	2a0003e1 	mov	w1, w0
  4009e8:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  4009ec:	9101e000 	add	x0, x0, #0x78
  4009f0:	97ffff08 	bl	400610 <printf@plt>
  4009f4:	97ffffd4 	bl	400944 <iii>
  4009f8:	2a0003e1 	mov	w1, w0
  4009fc:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400a00:	91026000 	add	x0, x0, #0x98
  400a04:	97ffff03 	bl	400610 <printf@plt>
  400a08:	97ffffc7 	bl	400924 <fxxx>
  400a0c:	2a0003e1 	mov	w1, w0
  400a10:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400a14:	9102e000 	add	x0, x0, #0xb8
  400a18:	97fffefe 	bl	400610 <printf@plt>
  400a1c:	97ffffcc 	bl	40094c <print_ix>
  400a20:	d503201f 	nop
  400a24:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400a28:	d65f03c0 	ret

0000000000400a2c <saaa>:
  400a2c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a30:	910003fd 	mov	x29, sp
  400a34:	9100c3a0 	add	x0, x29, #0x30
  400a38:	97ffff3d 	bl	40072c <test>
  400a3c:	97ffff69 	bl	4007e0 <test_pf>
  400a40:	97ffff68 	bl	4007e0 <test_pf>
  400a44:	97ffffd1 	bl	400988 <invoke>
  400a48:	52800000 	mov	w0, #0x0                   	// #0
  400a4c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400a50:	d65f03c0 	ret

0000000000400a54 <sbbb>:
  400a54:	a9b07bfd 	stp	x29, x30, [sp, #-256]!
  400a58:	910003fd 	mov	x29, sp
  400a5c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400a60:	91036000 	add	x0, x0, #0xd8
  400a64:	d2800101 	mov	x1, #0x8                   	// #8
  400a68:	97fffeea 	bl	400610 <printf@plt>
  400a6c:	b900ffbf 	str	wzr, [x29, #252]
  400a70:	1400000b 	b	400a9c <sbbb+0x48>
  400a74:	b940ffa0 	ldr	w0, [x29, #252]
  400a78:	12001c00 	and	w0, w0, #0xff
  400a7c:	11000400 	add	w0, w0, #0x1
  400a80:	12001c02 	and	w2, w0, #0xff
  400a84:	b980ffa0 	ldrsw	x0, [x29, #252]
  400a88:	910043a1 	add	x1, x29, #0x10
  400a8c:	38206822 	strb	w2, [x1, x0]
  400a90:	b940ffa0 	ldr	w0, [x29, #252]
  400a94:	11000400 	add	w0, w0, #0x1
  400a98:	b900ffa0 	str	w0, [x29, #252]
  400a9c:	b940ffa0 	ldr	w0, [x29, #252]
  400aa0:	71018c1f 	cmp	w0, #0x63
  400aa4:	54fffe8d 	b.le	400a74 <sbbb+0x20>
  400aa8:	b900f7bf 	str	wzr, [x29, #244]
  400aac:	b900ffbf 	str	wzr, [x29, #252]
  400ab0:	1400001d 	b	400b24 <sbbb+0xd0>
  400ab4:	b900fbbf 	str	wzr, [x29, #248]
  400ab8:	14000015 	b	400b0c <sbbb+0xb8>
  400abc:	b980f7a0 	ldrsw	x0, [x29, #244]
  400ac0:	910043a1 	add	x1, x29, #0x10
  400ac4:	38606823 	ldrb	w3, [x1, x0]
  400ac8:	b980fba2 	ldrsw	x2, [x29, #248]
  400acc:	b980ffa1 	ldrsw	x1, [x29, #252]
  400ad0:	aa0103e0 	mov	x0, x1
  400ad4:	d37df000 	lsl	x0, x0, #3
  400ad8:	8b010000 	add	x0, x0, x1
  400adc:	d37ff800 	lsl	x0, x0, #1
  400ae0:	910403a1 	add	x1, x29, #0x100
  400ae4:	8b000020 	add	x0, x1, x0
  400ae8:	8b020000 	add	x0, x0, x2
  400aec:	2a0303e1 	mov	w1, w3
  400af0:	3817a001 	sturb	w1, [x0, #-134]
  400af4:	b940f7a0 	ldr	w0, [x29, #244]
  400af8:	11000400 	add	w0, w0, #0x1
  400afc:	b900f7a0 	str	w0, [x29, #244]
  400b00:	b940fba0 	ldr	w0, [x29, #248]
  400b04:	11000400 	add	w0, w0, #0x1
  400b08:	b900fba0 	str	w0, [x29, #248]
  400b0c:	b940fba0 	ldr	w0, [x29, #248]
  400b10:	71003c1f 	cmp	w0, #0xf
  400b14:	54fffd4d 	b.le	400abc <sbbb+0x68>
  400b18:	b940ffa0 	ldr	w0, [x29, #252]
  400b1c:	11000400 	add	w0, w0, #0x1
  400b20:	b900ffa0 	str	w0, [x29, #252]
  400b24:	b940ffa0 	ldr	w0, [x29, #252]
  400b28:	7100141f 	cmp	w0, #0x5
  400b2c:	54fffc4d 	b.le	400ab4 <sbbb+0x60>
  400b30:	9101e3a0 	add	x0, x29, #0x78
  400b34:	f90077a0 	str	x0, [x29, #232]
  400b38:	b900ffbf 	str	wzr, [x29, #252]
  400b3c:	1400000c 	b	400b6c <sbbb+0x118>
  400b40:	f94077a0 	ldr	x0, [x29, #232]
  400b44:	91000401 	add	x1, x0, #0x1
  400b48:	f90077a1 	str	x1, [x29, #232]
  400b4c:	39400000 	ldrb	w0, [x0]
  400b50:	2a0003e1 	mov	w1, w0
  400b54:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400b58:	9103a000 	add	x0, x0, #0xe8
  400b5c:	97fffead 	bl	400610 <printf@plt>
  400b60:	b940ffa0 	ldr	w0, [x29, #252]
  400b64:	11000400 	add	w0, w0, #0x1
  400b68:	b900ffa0 	str	w0, [x29, #252]
  400b6c:	b940ffa0 	ldr	w0, [x29, #252]
  400b70:	71018c1f 	cmp	w0, #0x63
  400b74:	54fffe6d 	b.le	400b40 <sbbb+0xec>
  400b78:	528001a0 	mov	w0, #0xd                   	// #13
  400b7c:	97fffea9 	bl	400620 <putchar@plt>
  400b80:	52800000 	mov	w0, #0x0                   	// #0
  400b84:	a8d07bfd 	ldp	x29, x30, [sp], #256
  400b88:	d65f03c0 	ret

0000000000400b8c <sccc>:
  400b8c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b90:	910003fd 	mov	x29, sp
  400b94:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400b98:	91022000 	add	x0, x0, #0x88
  400b9c:	f9000fa0 	str	x0, [x29, #24]
  400ba0:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400ba4:	91022000 	add	x0, x0, #0x88
  400ba8:	f9000fa0 	str	x0, [x29, #24]
  400bac:	f9400fa0 	ldr	x0, [x29, #24]
  400bb0:	b9400001 	ldr	w1, [x0]
  400bb4:	f9400fa0 	ldr	x0, [x29, #24]
  400bb8:	b9400402 	ldr	w2, [x0, #4]
  400bbc:	f9400fa0 	ldr	x0, [x29, #24]
  400bc0:	91002003 	add	x3, x0, #0x8
  400bc4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400bc8:	9103c000 	add	x0, x0, #0xf0
  400bcc:	97fffe91 	bl	400610 <printf@plt>
  400bd0:	f9400fa0 	ldr	x0, [x29, #24]
  400bd4:	91007000 	add	x0, x0, #0x1c
  400bd8:	b9400001 	ldr	w1, [x0]
  400bdc:	f9400fa0 	ldr	x0, [x29, #24]
  400be0:	91007000 	add	x0, x0, #0x1c
  400be4:	b9400402 	ldr	w2, [x0, #4]
  400be8:	f9400fa0 	ldr	x0, [x29, #24]
  400bec:	91007000 	add	x0, x0, #0x1c
  400bf0:	91002003 	add	x3, x0, #0x8
  400bf4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400bf8:	9103c000 	add	x0, x0, #0xf0
  400bfc:	97fffe85 	bl	400610 <printf@plt>
  400c00:	52800000 	mov	w0, #0x0                   	// #0
  400c04:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c08:	d65f03c0 	ret

0000000000400c0c <print>:
  400c0c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c10:	910003fd 	mov	x29, sp
  400c14:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400c18:	91038000 	add	x0, x0, #0xe0
  400c1c:	b9400001 	ldr	w1, [x0]
  400c20:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400c24:	91038000 	add	x0, x0, #0xe0
  400c28:	39401000 	ldrb	w0, [x0, #4]
  400c2c:	2a0003e2 	mov	w2, w0
  400c30:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400c34:	91040000 	add	x0, x0, #0x100
  400c38:	97fffe76 	bl	400610 <printf@plt>
  400c3c:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400c40:	91038001 	add	x1, x0, #0xe0
  400c44:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400c48:	91038002 	add	x2, x0, #0xe0
  400c4c:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400c50:	91039003 	add	x3, x0, #0xe4
  400c54:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400c58:	91046000 	add	x0, x0, #0x118
  400c5c:	97fffe6d 	bl	400610 <printf@plt>
  400c60:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400c64:	91050000 	add	x0, x0, #0x140
  400c68:	d2800023 	mov	x3, #0x1                   	// #1
  400c6c:	d2800082 	mov	x2, #0x4                   	// #4
  400c70:	d2800101 	mov	x1, #0x8                   	// #8
  400c74:	97fffe67 	bl	400610 <printf@plt>
  400c78:	d503201f 	nop
  400c7c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c80:	d65f03c0 	ret

0000000000400c84 <priBit>:
  400c84:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400c88:	910003fd 	mov	x29, sp
  400c8c:	b9001fa0 	str	w0, [x29, #28]
  400c90:	52800400 	mov	w0, #0x20                  	// #32
  400c94:	b9002fa0 	str	w0, [x29, #44]
  400c98:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400c9c:	9105e000 	add	x0, x0, #0x178
  400ca0:	b9401fa1 	ldr	w1, [x29, #28]
  400ca4:	97fffe5b 	bl	400610 <printf@plt>
  400ca8:	1400000b 	b	400cd4 <priBit+0x50>
  400cac:	b9402fa0 	ldr	w0, [x29, #44]
  400cb0:	b9401fa1 	ldr	w1, [x29, #28]
  400cb4:	1ac02820 	asr	w0, w1, w0
  400cb8:	12000001 	and	w1, w0, #0x1
  400cbc:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400cc0:	91060000 	add	x0, x0, #0x180
  400cc4:	97fffe53 	bl	400610 <printf@plt>
  400cc8:	b9402fa0 	ldr	w0, [x29, #44]
  400ccc:	51000400 	sub	w0, w0, #0x1
  400cd0:	b9002fa0 	str	w0, [x29, #44]
  400cd4:	b9402fa0 	ldr	w0, [x29, #44]
  400cd8:	7100001f 	cmp	w0, #0x0
  400cdc:	54fffe8c 	b.gt	400cac <priBit+0x28>
  400ce0:	52800140 	mov	w0, #0xa                   	// #10
  400ce4:	97fffe4f 	bl	400620 <putchar@plt>
  400ce8:	d503201f 	nop
  400cec:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400cf0:	d65f03c0 	ret

0000000000400cf4 <_main>:
  400cf4:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400cf8:	910003fd 	mov	x29, sp
  400cfc:	f9000fbf 	str	xzr, [x29, #24]
  400d00:	97ffffc3 	bl	400c0c <print>
  400d04:	d0000080 	adrp	x0, 412000 <strlen@GLIBC_2.17>
  400d08:	91038000 	add	x0, x0, #0xe0
  400d0c:	f9000fa0 	str	x0, [x29, #24]
  400d10:	f9400fa0 	ldr	x0, [x29, #24]
  400d14:	b9400000 	ldr	w0, [x0]
  400d18:	97ffffdb 	bl	400c84 <priBit>
  400d1c:	f9400fa0 	ldr	x0, [x29, #24]
  400d20:	91001000 	add	x0, x0, #0x4
  400d24:	b9400000 	ldr	w0, [x0]
  400d28:	97ffffd7 	bl	400c84 <priBit>
  400d2c:	d503201f 	nop
  400d30:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400d34:	d65f03c0 	ret

0000000000400d38 <m_ain>:
  400d38:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400d3c:	910003fd 	mov	x29, sp
  400d40:	f90017bf 	str	xzr, [x29, #40]
  400d44:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400d48:	91066000 	add	x0, x0, #0x198
  400d4c:	910043a2 	add	x2, x29, #0x10
  400d50:	aa0003e3 	mov	x3, x0
  400d54:	a9400460 	ldp	x0, x1, [x3]
  400d58:	a9000440 	stp	x0, x1, [x2]
  400d5c:	f9400860 	ldr	x0, [x3, #16]
  400d60:	f9000840 	str	x0, [x2, #16]
  400d64:	910043a0 	add	x0, x29, #0x10
  400d68:	f90017a0 	str	x0, [x29, #40]
  400d6c:	f94017a1 	ldr	x1, [x29, #40]
  400d70:	f94017a0 	ldr	x0, [x29, #40]
  400d74:	b9401402 	ldr	w2, [x0, #20]
  400d78:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400d7c:	91062000 	add	x0, x0, #0x188
  400d80:	97fffe24 	bl	400610 <printf@plt>
  400d84:	97ffffdc 	bl	400cf4 <_main>
  400d88:	52800000 	mov	w0, #0x0                   	// #0
  400d8c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d90:	d65f03c0 	ret

0000000000400d94 <main>:
  400d94:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d98:	910003fd 	mov	x29, sp
  400d9c:	910063a0 	add	x0, x29, #0x18
  400da0:	d28003c2 	mov	x2, #0x1e                  	// #30
  400da4:	52800601 	mov	w1, #0x30                  	// #48
  400da8:	97fffe0a 	bl	4005d0 <memset@plt>
  400dac:	910063a2 	add	x2, x29, #0x18
  400db0:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400db4:	9106c001 	add	x1, x0, #0x1b0
  400db8:	aa0203e0 	mov	x0, x2
  400dbc:	a9400c22 	ldp	x2, x3, [x1]
  400dc0:	a9000c02 	stp	x2, x3, [x0]
  400dc4:	f9400822 	ldr	x2, [x1, #16]
  400dc8:	f9000802 	str	x2, [x0, #16]
  400dcc:	b8417021 	ldur	w1, [x1, #23]
  400dd0:	b8017001 	stur	w1, [x0, #23]
  400dd4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400dd8:	91074000 	add	x0, x0, #0x1d0
  400ddc:	d28003c1 	mov	x1, #0x1e                  	// #30
  400de0:	97fffe0c 	bl	400610 <printf@plt>
  400de4:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400de8:	9107a000 	add	x0, x0, #0x1e8
  400dec:	d2800201 	mov	x1, #0x10                  	// #16
  400df0:	97fffe08 	bl	400610 <printf@plt>
  400df4:	910063a0 	add	x0, x29, #0x18
  400df8:	f9001fa0 	str	x0, [x29, #56]
  400dfc:	f9401fa0 	ldr	x0, [x29, #56]
  400e00:	39400000 	ldrb	w0, [x0]
  400e04:	2a0003e1 	mov	w1, w0
  400e08:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e0c:	91080000 	add	x0, x0, #0x200
  400e10:	97fffe00 	bl	400610 <printf@plt>
  400e14:	f9401fa0 	ldr	x0, [x29, #56]
  400e18:	39400400 	ldrb	w0, [x0, #1]
  400e1c:	2a0003e1 	mov	w1, w0
  400e20:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e24:	91084000 	add	x0, x0, #0x210
  400e28:	97fffdfa 	bl	400610 <printf@plt>
  400e2c:	f9401fa0 	ldr	x0, [x29, #56]
  400e30:	91000801 	add	x1, x0, #0x2
  400e34:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e38:	91088000 	add	x0, x0, #0x220
  400e3c:	97fffdf5 	bl	400610 <printf@plt>
  400e40:	f9401fa0 	ldr	x0, [x29, #56]
  400e44:	91002001 	add	x1, x0, #0x8
  400e48:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e4c:	9108c000 	add	x0, x0, #0x230
  400e50:	97fffdf0 	bl	400610 <printf@plt>
  400e54:	f9401fa0 	ldr	x0, [x29, #56]
  400e58:	91000801 	add	x1, x0, #0x2
  400e5c:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e60:	91090000 	add	x0, x0, #0x240
  400e64:	97fffdeb 	bl	400610 <printf@plt>
  400e68:	f9401fa0 	ldr	x0, [x29, #56]
  400e6c:	91002001 	add	x1, x0, #0x8
  400e70:	b0000000 	adrp	x0, 401000 <_IO_stdin_used+0xd8>
  400e74:	91094000 	add	x0, x0, #0x250
  400e78:	97fffde6 	bl	400610 <printf@plt>
  400e7c:	97fffeec 	bl	400a2c <saaa>
  400e80:	52800000 	mov	w0, #0x0                   	// #0
  400e84:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400e88:	d65f03c0 	ret
  400e8c:	00000000 	.inst	0x00000000 ; undefined

0000000000400e90 <__libc_csu_init>:
  400e90:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400e94:	910003fd 	mov	x29, sp
  400e98:	a901d7f4 	stp	x20, x21, [sp, #24]
  400e9c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0xfda4>
  400ea0:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0xfda4>
  400ea4:	91374294 	add	x20, x20, #0xdd0
  400ea8:	913722b5 	add	x21, x21, #0xdc8
  400eac:	a902dff6 	stp	x22, x23, [sp, #40]
  400eb0:	cb150294 	sub	x20, x20, x21
  400eb4:	f9001ff8 	str	x24, [sp, #56]
  400eb8:	2a0003f6 	mov	w22, w0
  400ebc:	aa0103f7 	mov	x23, x1
  400ec0:	9343fe94 	asr	x20, x20, #3
  400ec4:	aa0203f8 	mov	x24, x2
  400ec8:	97fffdaa 	bl	400570 <_init>
  400ecc:	b4000194 	cbz	x20, 400efc <__libc_csu_init+0x6c>
  400ed0:	f9000bb3 	str	x19, [x29, #16]
  400ed4:	d2800013 	mov	x19, #0x0                   	// #0
  400ed8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400edc:	aa1803e2 	mov	x2, x24
  400ee0:	aa1703e1 	mov	x1, x23
  400ee4:	2a1603e0 	mov	w0, w22
  400ee8:	91000673 	add	x19, x19, #0x1
  400eec:	d63f0060 	blr	x3
  400ef0:	eb13029f 	cmp	x20, x19
  400ef4:	54ffff21 	b.ne	400ed8 <__libc_csu_init+0x48>  // b.any
  400ef8:	f9400bb3 	ldr	x19, [x29, #16]
  400efc:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400f00:	a942dff6 	ldp	x22, x23, [sp, #40]
  400f04:	f9401ff8 	ldr	x24, [sp, #56]
  400f08:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f0c:	d65f03c0 	ret

0000000000400f10 <__libc_csu_fini>:
  400f10:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400f14 <_fini>:
  400f14:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400f18:	910003fd 	mov	x29, sp
  400f1c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400f20:	d65f03c0 	ret
